1. Field of the Invention
The present invention relates to a data transmission apparatus and method for transmitting data in a delay-insensitive (DI) data transmission method supporting a handshake protocol, and more particularly, to a data transmission apparatus and method capable of reducing power consumption and complexity caused by a large number of wires in a large-scale system on chip (SoC) design, such as a globally asynchronous locally synchronous (GALS) system.
2. Discussion of Related Art
Currently, due to the development of semiconductor process technology and integrated circuit design technology, integrated circuit systems are designed in an SoC scheme implemented in units of chips.
Recently, with the further development of semiconductor process technology and integrated circuit design technology, the number of devices which can be integrated in one chip is gradually increasing, and as a result, the wiring structure of transmission lines designed in one chip is becoming more complicated.
Therefore, when integrated circuit systems are implemented in the SoC scheme, the number of wires, the lengths of the wires, signal delays caused by interference between the respective wires, etc. are very important design variables to be taken into consideration for normal operations of the overall chip.
Meanwhile, when a synchronous design using a global clock is applied to integrated circuit systems implemented in the SoC scheme, clock skew and jitter are caused by an increase in clock speed, a transmission delay of data is caused by an increase in the number and the lengths of transmission lines, and so on. These problems can be solved by applying an asynchronous design to integrated circuit systems implemented in the SoC scheme.
In the asynchronous design, no global clock is used, and data transmission is performed by a DI data transmission method supporting a handshake protocol which is irrelevant to a delay time.
By applying such an asynchronous design to the synchronous design, it is possible to solve the problems caused by the synchronous design. However, to implement such an asynchronous design, the design of an overall circuit becomes complicated, and a function of computer aided design (CAD) tools for an asynchronous design is insufficient.
Thus, to solve the problems of both the synchronous design and the asynchronous design at the same time, a GALS system has been proposed.
The GALS system basically does not use a global clock, and includes a plurality of locally synchronous (LS) modules which operate using clocks independent of each other. Data transmission between the respective LS modules is performed according to an asynchronous handshake protocol.
Since such a GALS system does not use a global clock, the problems of clock skew, jitter, etc. are solved. Also, data transmission between LS modules which operate at different timings is performed by the DI data transmission method, and thus it is possible to secure stable data transmission.
In the DI data transmission method, data is expressed using encoding schemes, such as dual-rail encoding and 1-of-4 encoding, and a 4-phase handshaking protocol is used like in an existing synchronous design.
According to the 4-phase handshaking protocol, data is basically expressed as a binary value of a return to zero (RZ) type. In other words, in the 4-phase handshaking protocol, there is a space state for distinguishing continuous data. Since the space state has the same latency as data, a 2-phase handshaking protocol method having no space state is more effective than the 4-phase handshaking protocol method in the GALS system in which data transmission frequently occurs.
According to the 2-phase handshaking protocol based on a dual-rail, which is known as a level-encoded 2-phase dual-rail (LEDR), one wire is encoded with data and the other wire is encoded with a phase change. This is different from an existing dual-rail-based 2-phase protocol in which data transmission of “0” and “1” is encoded with state changes of the respective two wires. In other words, data of “0” and “1” are encoded not with a state change but with a level in one wire, and distinctions between data are made with a change of the other wire.
As a result, an XOR value of the two wires changes every time data is transmitted, and this is detected to determine validity of data. Since the LEDR is not necessary to decode data, the LEDR has higher performance and less design complexity than the existing dual-rail-based 2-phase protocol. However, since 2N+1 wires are required for N-bit data transmission, performance, power consumption, and design complexity of the LEDR are degraded due to the increased number of wires.
A variety of technologies for reducing the number of wires is currently under development, and representatively, the following previous literature has been disclosed.
(1) “New signal transmitting and receiving device for wiring system” (Korean Patent Application No. 10-1997-0018460)
The above previous literature proposes a method of simultaneously transmitting several different kinds of signals through one wire among a plurality of function blocks in an integrated circuit to reduce an area occupied by wires.
According to the previous literature, theoretically, while N-bit data is transmitted, 2N voltage values having a triangular pulse shape are encoded and transmitted through one wire, and a receiver circuit receives the encoded data and restores the encoded data to the N-bit data. Therefore, the number of wires necessary for wiring is reduced, such that the area of an integrated circuit can be reduced.
However, as the number of voltage values which are encodable in a wire increases, the number of kinds of logic to be decoded increases. As a result, the complexity of a receiver circuit remarkably increases, and thus the number of wires that can be reduced is limited.
Also, in a trend toward lowering a supply voltage in an integrated circuit, the current-mode multi-valued logic circuit technology for expressing a plurality of states using a voltage which is used in the previous literature may degrade a noise margin characteristic of a voltage in a receiver circuit.
Further, the previous literature does not support a handshake protocol necessary for DI data transmission, and thus cannot be applied to a GALS system.
(2) “Delay-insensitive data transfer circuit using current-mode multi-valued logic (Korean Patent Application No. “10-2004-0011299)” and “Low static powered delay-insensitive data transfer apparatus (Korean Patent Application No. 10-2006-0119056)”
Unlike the aforementioned previous literature (Korean Patent Application No. 10-1997-018460), the previous literature (Korean Patent Application No. 10-2004-0011299) proposes a protocol which supports a handshake protocol and employs a ternary encoding method to reduce the number of wires.
According to the previous literature (Korean Patent Application No. 10-2004-0011299), it is possible to express three kinds of logic in one wire using a current-mode multi-valued logic circuit without affecting the noise margin of a supply voltage, and thus a circuit for N-bit data transmission can be designed with N+1 wires.
Also, according to the previous literature (Korean Patent Application No. 10-2006-0119056), power consumption in a standby state is drastically reduced by complementing a high static current consumption characteristic of an existing current-mode DI transmission method.
However, according to the two data transmission methods using a current-mode circuit (Korean Patent Application Nos. 10-2004-0011299 and 10-2006-0119056), N inputs are encoded with N+1 wires, and thus the two data transmission methods are not satisfactory in terms of a reduction in the number of wires.
(3) “Data transmission device, data receiving device, data transmitting system, and method for transmitting data (Korean Patent Application No. “10-2008-0119279)”
The previous literature proposes a 2-phase signaling technique of a current-mode DI transmission method. According to the previous literature, in order for an encoder to compare currently input data with the next data, synchronization between an input request signal and a data signal is assumed, and a delay element is inserted into the data signal to extract delayed current data from the next request signal.
However, when an encoder is designed on only synchronization assumption that a data signal should be stabilized prior to a request signal in an asynchronous signal environment, a designer is required to know the largest time difference between an input request signal and a data signal and the shortest period of request signals.
This may make it very difficult to determine a delay time of a delay element, and in some cases (the largest time difference between an input request signal and a data signal > the shortest period of request signals), it may not be possible to find a satisfactory delay time of a delay element. This means that it is not possible to ensure the functionality of an encoder.
According to the previous literature (Korean Patent Application No. 10-2008-0119279), a decoder uses a D flip-flop to restore a data signal, and additional logic for providing a data capturing time point of the device, that is, a clock signal of the device, is necessary.
Also, the previous literature (Korean Patent Application No. 10-2008-0119279) does not proposes a method of reducing the latency of data transmission through a long wire, such as buffer insertion, used in binary data transmission based on a voltage mode. In other words, implementation is complicated.
Further, according to the previous literature (Korean Patent Application No. 10-2008-0119279), N inputs are encoded with N+1 wires, like in the above-described previous literature, and thus the previous literature (Korean Patent Application No. 10-2008-0119279) is not satisfactory in terms of a reduction in the number of wires.